1. Field of the Invention
The present invention relates to a page buffer for an NAND flash memory and, more specifically, to a pager buffer for an NAND flash memory capable of improving data loading speed depending on contents of data to be programmed.
2. Discussion of Related Art
Recently, demands for semiconductor memory devices capable of electrically programming, erasing and storing data, even in case that a power source is not supplied, has been increased. Further, in order to develop a large capacity memory device capable of storing an amount of data, a high-integration technology of a memory cell has been developed. As a result, an NAND type of a flash memory device, in which a plurality of memory cells are serially connected to constitute one string and a memory cell array includes a plurality of strings, has been proposed.
A flash memory cell of the NAND flash memory device comprise a current path formed between a source and a drain on a semiconductor substrate, and a floating gate and a control gate formed between insulating layers on the semiconductor substrate. A programming operation of the flash memory cell is generally accomplished by grounding the source and the drain areas of the memory cell and the semiconductor substrate of a bulk area, and applying a high positive voltage (program voltage; Vpp, for example, 15V˜20V) to a control gate to generate fowler-nordheim tunneling (referred to as “F-N tunneling”) between a floating gate and the semiconductor substrate. The F-N tunneling means that electrons of the bulk area are accumulated on the floating gate by an electric field of the high voltage (Vpp) applied to the control gate to increase a threshold voltage of the memory cell.
An erasing operation of the flash memory cell is concurrently performed in unit of sectors sharing the bulk area, by applying a high negative voltage (erase voltage: Vera, for example, −10V) to the control gate and a predetermined voltage (for example, 5V) to the bulk area to generate the F-N tunneling. By the F-N tunneling, electrons accumulated on the floating gate are discharged into the source area, so that the flash memory cells have an erasing threshold voltage distribution in the range of approximately ‘−2V to −3V’. In the cell of which the threshold voltage is heightened by the programming operation, since the current flowing from the drain area to the source area is prevented during a read-out operation, it seems like that the cell is turned-off. On the other hand, in the cell of which the threshold voltage is dropped down by the erasing operation, since the current flowing from the drain area to the source area is available, it seems like that the cell is turned-on.
A general NAND flash memory device comprises a memory cell array, a page buffer and a column decoder. In addition, the general NAND flash memory device further comprises a control logic unit, a row decoder, an address buffer, or the like. The memory cell array includes a plurality of memory cell strings connected to a plurality of bit lines, which are extended in a column direction.
Each memory cell string has a plurality of floating gate type memory cells serially connected to each other. A plurality of word lines are extended in a row direction, and the control gate of each memory cell is connected to the corresponding the word line. The page buffer comprises a plurality of page buffers connected between the bit lines and the column decoder. The column decoder is connected between the page buffer and the data lines.
FIG. 1 is a circuit diagram of a conventional page buffer for an NAND flash memory.
In order to load data to a first latch 10, a data line discharging signal DL_DIS of FIG. 2A is activated in a high level. Therefore, an NMOS transistor N7 is turned-on to discharge charges of the corresponding data line. A data input DI or nDI of the page buffer to be selected depending on a desired column address Y-ADDRESS is enabled depending on the data (having a high level or a low level) to be input.
For example, when the data input DI is in a high level, an NMOS transistor N1 is turned-on, so that voltage of a node Q1 of the first latch 10 becomes a high level. On the contrary, when the data input nDI is in a high level, an NMOS transistor N8 is turned-on, so that voltage of the node Q1 becomes a low level.
Procedures of transferring data will be described referring to FIG. 2B.
When a main reset bar signal MRSTb drops down to a low level, a PMOS transistor P3 is turned-on, so that a node K1 becomes a high level. Therefore, an output Q2 of a second latch 30 is maintained in a low level. When a precharge bar signal PRECHb drops down to a low level, a PMOS transistor P2 is turned-on to maintain a gate of an NMOS transistor N10 in a high level. At that time, if a page dump signal PDUMP is in a high level, data stored on the first latch 10 is transferred to a gate terminal of an NMOS transistor N9. When a main latch signal MLCH is in a high level, the gate of the NMOS transistor N10 is maintained in a high level. When an output of the first latch 10 is in a high level, the NMOS transistor N9 is turned-on, and then the NMOS transistor N10 is turned-on for the period of the main latch signal MLCH being in a high level, so that a voltage of the node K1 becomes a low level. Therefore, the second latch 30 stores a high level. In other words, the data of the first latch 10 is transferred to the second latch 30.
After transferring, the bit line selection signal BLSLT is in a high level, the NMOS transistor N2 is turned-on to transfer the data stored on the second latch 30 to the memory cell through the bit line.
The read-out operation of the memory cell will be described, as follows.
The NMOS transistor N2 is turned-on depending on the bit line selection signal, so that the data stored on the memory cell is stored on the second latch 30. When a page buffer data output signal PBDO is activated, the NMOS transistor N1 is turned-on, so that the data stored on the second latch 30 is transferred to the data line through the column selector (Y-selector) 20.
In the aforementioned conventional page buffer, since the data loading operation is carried out from the first address to the last address regardless of contents of data to be programmed when loading data, the NMOS transistors receiving the data input DI, nDI as a control signal are required. Thus, there is a problem that a chip area becomes larger because of area occupied by the NMOS transistors.